The present invention generally relates to semiconductor devices, more particularly to a high current semiconductor device SOIC package.
Power semiconductor packages have evolved from through hole to surface mounted packages with the evolution of printed circuit board technology. Surface mounted packages generally include a lead frame on which a semiconductor device is mounted. The semiconductor device and a portion of the lead frame are generally encapsulated with a resin material. In a leaded package, lead terminals extend outside the resin body and include bonding pads for providing a wire bond connection from the semiconductor device to the lead terminal.
Major considerations in the packaging of semiconductor devices include high thermal dissipation, low parasitic inductance, low electrical resistance between the semiconductor device and the circuit environment, good reliability in terms of thermal cycling and thermal shock/fatigue, and minimal consumption of circuit board space.
Conventional power semiconductor packages include Small Outline Integrated Circuits (SOIC) packages with between 8 and 32 lead counts. In high current applications, conventional SOIC packages suffer from poor thermal performance due to lead frame thickness and package bottom encapsulation. Furthermore, semiconductor dies are conventionally attached to SOIC package lead frames using thermally poor materials such as Ag epoxy.
The use of conventional SOIC packages in many applications is further limited as the SOIC package footprint does not match the TO 252 (DPAK) land pattern on printed circuit boards. Additionally, conventional SOIC packages have an easily deformable lead frame resulting in lower assembly yield and relatively small wire bonding areas which limit the number of bonding wires that can be used to thereby reduce package electrical resistance.